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A Versatile Accelerator Design for Multiple Deep Neural Network Applications
Deep Neural Networks (DNNs) have become integral to numerous applications, from image recognition to video processing, touching almost every aspect of modern life. The expansion of DNN applications has led to increasing demands on underlying hardware architectures, particularly in terms of memory bandwidth and communication requirements. Despite numerous...
Published: 2/18/2025
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Inventor(s): Jiaqi Yang, Hao Zheng, Ahmed Louri
Keywords(s):
Category(s): Technology Classifications, Technology Classifications > Computers Electronics & Software, Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
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EZ-PASS: An Energy & Performance-Efficient Power-gating Router Architecture for Scalable NoCs
Researchers at GW have developed a novel router architecture that is capable of being implemented on various networking applications. The router architecture can be used for high-performance communication which only consumes little energy while still providing high speed. This architecture has a greater impact on applying power-gating for various interconnects...
Published: 2/18/2025
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Inventor(s): Ahmed Louri, Hao Zheng
Keywords(s):
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
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Network Design for Chiplet-based Manycore Architecture
Researchers at The George Washington University are developing a flexible interconnection network design, called Adapt-Net, for chiplet-based manycore architectures. The goal of Adapt-Net is to support the concurrent communication of diverse applications running at the same time, improving the energy-efficiency and performance of the manycore architecture....
Published: 2/18/2025
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Inventor(s): Hao Zheng, Ke Wang, Ahmed Louri
Keywords(s):
Category(s): Technology Classifications > Computers Electronics & Software, Technology Classifications > Computers Electronics & Software > Computing Architecture
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Learning-Based High-Performance, Energy-Efficient, and Secure Interconnection Design Framework
Researchers at the George Washington University have invented a novel network-on-chip framework, named TSA-NoC, which significantly improves on-chip security. The invented framework also minimizes the latency and cost of security techniques for simultaneously improving system-level performance and power.
As the market for parallel computing is growing...
Published: 4/3/2025
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Inventor(s): Ke Wang, Hao Zheng, Ahmed Louri
Keywords(s):
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
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