Researchers at GW have developed a novel router architecture that is capable of being implemented on various networking applications. The router architecture can be used for high-performance communication which only consumes little energy while still providing high speed. This architecture has a greater impact on applying power-gating for various interconnects in many-core, GPU, and heterogeneous systems. Further, in comparison with conventional power-gating techniques, this router architecture can provide more flexible bypassing functions which allows flits go through multiple ports to multiple output ports. This translates to lesser latency and more energy savings. The disclosed solution can be easily reproduced and can provide superior scalability for various architecture designs.
The disclosed invention can be implemented as either a system, a method, or as a device as can be appreciated. The system or method or device can include various aspects as follows: (i) an input port module capable of identifying and indicating an input port associated with an incoming flit; (ii) a downstream router status module configured to indicate a power status of a downstream router. In an embodiment, when an incoming flit arrives while the router is powered off, the flit can be passed to a network interface (NI) for processing. In another embodiment, it can take three cycles to process a flit. In an embodiment, the current router can record a relevant credit number (as can be appreciated) associated with a downstream router.
Fig. 1 – Aspects of the disclosed Invention
Applications:
- Networking applications
- Routers in many-core, GPU, and heterogeneous systems
- Network-on-chips
Advantages:
- High Speed
- Energy-efficient
- Higher flexibility in bypassing power
- Less latency in flit transmission
- Superior scalability
