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A Resilient, Adaptive, Multi-Context Switching, Energy-Efficient Spintronic FPGA (RAMSES-FPGA)

Static random-access memories (SRAM) based FPGAs are susceptible to Single Event Upsets (SEUs). SEUs are transient faults caused by high-energy particles striking the semiconductor material which result in unintended changes in the stored data. This vulnerability is a significant concern specifically in environments with high levels of radiation, such...

Published: 7/28/2025 | Inventor(s): Abdolah Amirany, Samuel Farid, Hamidreza Imani Porshokouh, Tarek El-Ghazawi

Keywords(s):

Category(s): Technology Classifications > Computers Electronics & Software, Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips

ESSRA: An Efficient Spintronic Stochastic Reconfigurable Architecture

Recent research in Stochastic Computing (SC) is focused on practical methods for bitstream generation, optimizing logic operations for stochastic data, and developing architectures that natively support SC. This approach has proven particularly promising in simplifying and accelerating complex computations in fields such as AI and image processing....

Published: 7/28/2025 | Inventor(s): Abdolah Amirany, Hamidreza Imani Porshokouh, Samuel Farid, Tarek El-Ghazawi

Keywords(s):

Category(s): Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips